Add Tercel PHY reset synchronization

[microwatt.git] / dcache_tb.vhdl

diff --git a/dcache_tb.vhdl b/dcache_tb.vhdl
index 0edbdb7a45a1469b84956fda566e9471f8d6886b..1e2e07b7be13c5495d6bec3962bd2e0a1f89bb24 100644 (file)
--- a/dcache_tb.vhdl
+++ b/dcache_tb.vhdl
@@ -13,7 +13,10 @@ architecture behave of dcache_tb is
     signal rst          : std_ulogic;
 
     signal d_in         : Loadstore1ToDcacheType;
-    signal d_out        : DcacheToWritebackType;
+    signal d_out        : DcacheToLoadstore1Type;
+
+    signal m_in         : MmuToDcacheType;
+    signal m_out        : DcacheToMmuType;
 
     signal wb_bram_in   : wishbone_master_out;
     signal wb_bram_out  : wishbone_slave_out;
@@ -30,14 +33,16 @@ begin
             rst => rst,
             d_in => d_in,
             d_out => d_out,
+            m_in => m_in,
+            m_out => m_out,
             wishbone_out => wb_bram_in,
             wishbone_in => wb_bram_out
             );
 
     -- BRAM Memory slave
-    bram0: entity work.mw_soc_memory
+    bram0: entity work.wishbone_bram_wrapper
         generic map(
-            MEMORY_SIZE   => 128,
+            MEMORY_SIZE   => 1024,
             RAM_INIT_FILE => "icache_test.bin"
             )
         port map(
@@ -71,12 +76,9 @@ begin
        d_in.nc <= '0';
        d_in.addr <= (others => '0');
        d_in.data <= (others => '0');
-       d_in.write_reg <= (others => '0');
-       d_in.length <= (others => '0');
-       d_in.byte_reverse <= '0';
-       d_in.sign_extend <= '0';
-       d_in.update <= '0';
-       d_in.update_reg <= (others => '0');
+        m_in.valid <= '0';
+        m_in.addr <= (others => '0');
+        m_in.pte <= (others => '0');
 
         wait for 4*clk_period;
        wait until rising_edge(clk);
@@ -89,11 +91,10 @@ begin
        wait until rising_edge(clk);
         d_in.valid <= '0';
 
-       wait until rising_edge(clk) and d_out.write_enable = '1';
-        assert d_out.valid = '1';
-        assert d_out.write_data = x"0000000100000000"
+       wait until rising_edge(clk) and d_out.valid = '1';
+        assert d_out.data = x"0000000100000000"
            report "data @" & to_hstring(d_in.addr) &
-           "=" & to_hstring(d_out.write_data) &
+           "=" & to_hstring(d_out.data) &
            " expected 0000000100000000"
            severity failure;
 --      wait for clk_period;
@@ -106,11 +107,10 @@ begin
        wait until rising_edge(clk);
         d_in.valid <= '0';
 
-       wait until rising_edge(clk) and d_out.write_enable = '1';
-        assert d_out.valid = '1';
-        assert d_out.write_data = x"0000000D0000000C"
+       wait until rising_edge(clk) and d_out.valid = '1';
+        assert d_out.data = x"0000000D0000000C"
            report "data @" & to_hstring(d_in.addr) &
-           "=" & to_hstring(d_out.write_data) &
+           "=" & to_hstring(d_out.data) &
            " expected 0000000D0000000C"
            severity failure;
 
@@ -121,19 +121,18 @@ begin
         d_in.valid <= '1';
        wait until rising_edge(clk);
        d_in.valid <= '0';
-
-       wait until rising_edge(clk) and d_out.write_enable = '1';
-        assert d_out.valid = '1';
-        assert d_out.write_data = x"0000004100000040"
+       wait until rising_edge(clk) and d_out.valid = '1';
+        assert d_out.data = x"0000004100000040"
            report "data @" & to_hstring(d_in.addr) &
-           "=" & to_hstring(d_out.write_data) &
+           "=" & to_hstring(d_out.data) &
            " expected 0000004100000040"
            severity failure;
 
-       wait for clk_period*4;
-
-        assert false report "end of test" severity failure;
-        wait;
+       wait until rising_edge(clk);
+       wait until rising_edge(clk);
+       wait until rising_edge(clk);
+       wait until rising_edge(clk);
 
+       std.env.finish;
     end process;
 end;