Merge pull request #130 from riscv/trap_entry_align-1

[riscv-tests.git] / debug / programs / entry.S

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index a2ea955a2707ed93d1283b066d801fc46ac2d398..6d84718f0388769e9f7140b733638d7a253ead48 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -1,8 +1,6 @@
 #include "encoding.h"
 
-// Enough stack to store every register in case a trap handler is executed,
-// plus 33 more values.
-#define STACK_SIZE (64 * XLEN / 8)
+#define STACK_SIZE (90 * XLEN / 8)
 
 #if XLEN == 64
 # define LREG ld
@@ -108,6 +106,7 @@ wait_until_initialized:      # Wait for hart 0 to perform initialization.
   j     _init
 
 
+.align 2
 trap_entry:
   addi sp, sp, -32*REGBYTES