Use `gdb_report_register_access_error enable`

[riscv-tests.git] / debug / targets / RISC-V / spike-1.cfg

diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index fc20b53b4341ff600c6ef375cad8660460793df9..083794fc14906a9fd9b133810371ba373bc20fbe 100644 (file)
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -11,6 +11,15 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
 
 init
-reset halt
+
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt