Merge pull request #156 from riscv/PrivChange

[riscv-tests.git] / debug / targets / RISC-V / spike-2.cfg

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 114d5b880b953861066d045b20112535226c9477..9dbbfe30911923bdd1b11599f8be8dff6d601b7d 100644 (file)
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -14,10 +14,12 @@ target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.
 riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
 
 init