Add test case for `riscv expose_custom`.
[riscv-tests.git] / debug / targets / RISC-V / spike32.py
index fc7d598c9ff4fc3c88883a84eb01b8a7e9bffd35..a831ecbb2af2ae63d9e5a0cbcfbe870885cefa0b 100644 (file)
@@ -6,13 +6,15 @@ class spike32_hart(targets.Hart):
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
-    link_script_path = "spike64.lds"
+    reset_vectors = [0x1000]
+    link_script_path = "spike32.lds"
 
 class spike32(targets.Target):
     harts = [spike32_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
+    implements_custom_test = True
 
     def create(self):
-        return testlib.Spike(self)
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDC")