Change Spike's RAM location to match the linker script

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index 538caaf41d6dadcc5b4f47770b7b3b33051c79a5..423ff6955f3c64cc968d6a44a2a203a902bc8463 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -12,10 +12,11 @@ class Target(object):
     temporary_binary = None
     openocd_config = []
     use_fpu = False
+    misa = None
 
-    def __init__(self, cmd, run, isolate):
-        self.cmd = cmd
-        self.run = run
+    def __init__(self, server_cmd, sim_cmd, isolate):
+        self.server_cmd = server_cmd
+        self.sim_cmd = sim_cmd
         self.isolate = isolate
 
     def target(self):
@@ -25,7 +26,7 @@ class Target(object):
     def server(self):
         """Start the debug server that gdb connects to, eg. OpenOCD."""
         if self.openocd_config:
-            return testlib.Openocd(cmd=self.cmd, config=self.openocd_config)
+            return testlib.Openocd(server_cmd=self.server_cmd, config=self.openocd_config)
         else:
             raise NotImplementedError
 
@@ -39,9 +40,11 @@ class Target(object):
                     prefix=binary_name + "_")
             binary_name = self.temporary_binary.name
             Target.temporary_files.append(self.temporary_binary)
-        march = "RV%dIMA" % self.xlen
+        march = "rv%dima" % self.xlen
         if self.use_fpu:
-            march += "FD"
+            march += "fd"
+        if self.extensionSupported("c"):
+            march += "c"
         testlib.compile(sources +
                 ("programs/entry.S", "programs/init.c",
                     "-I", "../env",
@@ -49,31 +52,38 @@ class Target(object):
                     "-T", "targets/%s/link.lds" % (self.directory or self.name),
                     "-nostartfiles",
                     "-mcmodel=medany",
+                    "-DXLEN=%d" % self.xlen,
                     "-o", binary_name),
                 xlen=self.xlen)
         return binary_name
 
+    def extensionSupported(self, letter):
+        # target.misa is set by testlib.ExamineTarget
+        return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+
 class SpikeTarget(Target):
     # pylint: disable=abstract-method
     directory = "spike"
-    ram = 0x80010000
-    ram_size = 5 * 1024 * 1024
+    ram = 0x10000000
+    ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
+    openocd_config = "targets/%s/openocd.cfg" % directory
 
 class Spike64Target(SpikeTarget):
     name = "spike64"
     xlen = 64
+    use_fpu = True
 
-    def server(self):
-        return testlib.Spike(self.cmd, halted=True)
+    def target(self):
+        return testlib.Spike(self.sim_cmd)
 
 class Spike32Target(SpikeTarget):
     name = "spike32"
     xlen = 32
 
-    def server(self):
-        return testlib.Spike(self.cmd, halted=True, xlen=32)
+    def target(self):
+        return testlib.Spike(self.sim_cmd, xlen=32)
 
 class FreedomE300Target(Target):
     name = "freedom-e300"
@@ -83,17 +93,21 @@ class FreedomE300Target(Target):
     instruction_hardware_breakpoint_count = 2
     openocd_config = "targets/%s/openocd.cfg" % name
 
+class HiFive1Target(FreedomE300Target):
+    name = "HiFive1"
+    openocd_config = "targets/%s/openocd.cfg" % name
+
 class FreedomE300SimTarget(Target):
     name = "freedom-e300-sim"
     xlen = 32
-    timeout_sec = 240
+    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.run, debug=False)
+        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
 
 class FreedomU500Target(Target):
     name = "freedom-u500"
@@ -106,14 +120,14 @@ class FreedomU500Target(Target):
 class FreedomU500SimTarget(Target):
     name = "freedom-u500-sim"
     xlen = 64
-    timeout_sec = 240
+    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.run, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 targets = [
         Spike32Target,
@@ -121,18 +135,19 @@ targets = [
         FreedomE300Target,
         FreedomU500Target,
         FreedomE300SimTarget,
-        FreedomU500SimTarget]
+        FreedomU500SimTarget,
+        HiFive1Target]
 
 def add_target_options(parser):
     group = parser.add_mutually_exclusive_group(required=True)
     for t in targets:
         group.add_argument("--%s" % t.name, action="store_const", const=t,
                 dest="target")
-    parser.add_argument("--run",
+    parser.add_argument("--sim_cmd",
             help="The command to use to start the actual target (e.g. "
             "simulation)")
-    parser.add_argument("--cmd",
-            help="The command to use to start the debug server.")
+    parser.add_argument("--server_cmd",
+            help="The command to use to start the debug server (e.g. OpenOCD)")
 
     xlen_group = parser.add_mutually_exclusive_group()
     xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",