Change Spike's RAM location to match the linker script

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index d49b3970670598768fe7cac5dd56bbae79dd7b4f..423ff6955f3c64cc968d6a44a2a203a902bc8463 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -64,8 +64,8 @@ class Target(object):
 class SpikeTarget(Target):
     # pylint: disable=abstract-method
     directory = "spike"
-    ram = 0x80010000
-    ram_size = 5 * 1024 * 1024
+    ram = 0x10000000
+    ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
     openocd_config = "targets/%s/openocd.cfg" % directory
@@ -76,14 +76,14 @@ class Spike64Target(SpikeTarget):
     use_fpu = True
 
     def target(self):
-        return testlib.Spike(self.sim_cmd, halted=True)
+        return testlib.Spike(self.sim_cmd)
 
 class Spike32Target(SpikeTarget):
     name = "spike32"
     xlen = 32
 
     def target(self):
-        return testlib.Spike(self.sim_cmd, halted=True, xlen=32)
+        return testlib.Spike(self.sim_cmd, xlen=32)
 
 class FreedomE300Target(Target):
     name = "freedom-e300"
@@ -127,7 +127,7 @@ class FreedomU500SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 targets = [
         Spike32Target,