debug: Correct the calling for a 32-bit simulation target

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index a69f43d91463924ccee841d7f9aaaac640710a7b..b8557ce5748e3103a515d823ee68895b63f0f483 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -64,8 +64,8 @@ class Target(object):
 class SpikeTarget(Target):
     # pylint: disable=abstract-method
     directory = "spike"
-    ram = 0x80010000
-    ram_size = 5 * 1024 * 1024
+    ram = 0x10000000
+    ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
     openocd_config = "targets/%s/openocd.cfg" % directory
@@ -107,7 +107,7 @@ class FreedomE300SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 class FreedomU500Target(Target):
     name = "freedom-u500"
@@ -127,7 +127,7 @@ class FreedomU500SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 targets = [
         Spike32Target,