Merge remote-tracking branch 'origin/newprogram' into debug-0.13

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index bcebc0b613ef83797a01fc4dc7d9d77370bf0223..f2728d1aed30db7ff7cdecf1f100e026f06d1577 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -68,20 +68,21 @@ class SpikeTarget(Target):
     ram_size = 5 * 1024 * 1024
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
+    openocd_config = "targets/%s/openocd.cfg" % directory
 
 class Spike64Target(SpikeTarget):
     name = "spike64"
     xlen = 64
     use_fpu = True
 
-    def server(self):
+    def target(self):
         return testlib.Spike(self.cmd, halted=True)
 
 class Spike32Target(SpikeTarget):
     name = "spike32"
     xlen = 32
 
-    def server(self):
+    def target(self):
         return testlib.Spike(self.cmd, halted=True, xlen=32)
 
 class FreedomE300Target(Target):
@@ -92,10 +93,14 @@ class FreedomE300Target(Target):
     instruction_hardware_breakpoint_count = 2
     openocd_config = "targets/%s/openocd.cfg" % name
 
+class HiFive1Target(FreedomE300Target):
+    name = "HiFive1"
+    openocd_config = "targets/%s/openocd.cfg" % name
+
 class FreedomE300SimTarget(Target):
     name = "freedom-e300-sim"
     xlen = 32
-    timeout_sec = 240
+    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
@@ -115,7 +120,7 @@ class FreedomU500Target(Target):
 class FreedomU500SimTarget(Target):
     name = "freedom-u500-sim"
     xlen = 64
-    timeout_sec = 240
+    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
@@ -130,7 +135,8 @@ targets = [
         FreedomE300Target,
         FreedomU500Target,
         FreedomE300SimTarget,
-        FreedomU500SimTarget]
+        FreedomU500SimTarget,
+        HiFive1Target]
 
 def add_target_options(parser):
     group = parser.add_mutually_exclusive_group(required=True)