Add Tercel PHY reset synchronization

[microwatt.git] / dmi_dtm_tb.vhdl

diff --git a/dmi_dtm_tb.vhdl b/dmi_dtm_tb.vhdl
index fe60c12356d3412ac3c06ca3f35730dd594ce1b2..069426650e3039cbb0acd36fd93fae39d97a208b 100644 (file)
--- a/dmi_dtm_tb.vhdl
+++ b/dmi_dtm_tb.vhdl
@@ -50,8 +50,8 @@ begin
            dmi_ack     => dmi_ack
            );
 
-    simple_ram_0: entity work.mw_soc_memory
-       generic map(RAM_INIT_FILE => "simple_ram_behavioural.bin",
+    simple_ram_0: entity work.wishbone_bram_wrapper
+       generic map(RAM_INIT_FILE => "main_ram.bin",
                    MEMORY_SIZE => 524288)
        port map(clk => clk, rst => rst,
                 wishbone_in => wishbone_ram_out,