Add Tercel PHY reset synchronization

[microwatt.git] / dmi_dtm_xilinx.vhdl

diff --git a/dmi_dtm_xilinx.vhdl b/dmi_dtm_xilinx.vhdl
index 6e47c569876c09ac84e0bad421eda422175a6754..69d8996073c09795ee096e96fb7a8466dc512828 100644 (file)
--- a/dmi_dtm_xilinx.vhdl
+++ b/dmi_dtm_xilinx.vhdl
@@ -127,6 +127,11 @@ architecture behaviour of dmi_dtm is
     constant DMI_RSP_OK  : std_ulogic_vector(1 downto 0) := "00";
     constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
 
+    attribute ASYNC_REG : string;
+    attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
+    attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
+    attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
+    attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
 begin
 
     -- Implement the Xilinx bscan2 for series 7 devices (TODO: use PoC to
@@ -161,7 +166,6 @@ begin
            O => jtag_clk
            );
 
-
     -- dmi_req synchronization
     dmi_req_sync : process(sys_clk)
     begin
@@ -218,11 +222,12 @@ begin
     -- jtag_req latch. Could be split into 3 processes but it's probably
     -- not worthwhile.
     --
-    shifter: process(jtag_clk, jtag_reset)
+    shifter: process(jtag_clk, jtag_reset, sys_reset)
     begin
-       if jtag_reset = '1' then
+       if jtag_reset = '1' or sys_reset = '1' then
            shiftr <= (others => '0');
            jtag_req <= '0';
+           request <= (others => '0');
        elsif rising_edge(jtag_clk) then
 
            -- Handle jtag "commands" when sel is 1