Add Tercel PHY reset synchronization

[microwatt.git] / dram_tb.vhdl

diff --git a/dram_tb.vhdl b/dram_tb.vhdl
index 571bd70bda32661b1c1b00db52da155d6464d41b..ca7c90b82a9ff54fabc2338cbe24fb16d302b56c 100644 (file)
--- a/dram_tb.vhdl
+++ b/dram_tb.vhdl
@@ -44,6 +44,7 @@ begin
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
             DRAM_DLINES => 16,
+            DRAM_CKLINES => 1,
             DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => DRAM_INIT_SIZE