Reflect changes to ISA

[riscv-tests.git] / env / pt / riscv_test.h

diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h
index b0ec8d7f17d50dd6cd9f2056ce2eb413b384e586..822dcfaebb876281e98e9d616f5ada2206500428 100644 (file)
--- a/env/pt/riscv_test.h
+++ b/env/pt/riscv_test.h
@@ -1,70 +1,22 @@
 #ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
 #define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
 
-#include "pcr.h"
+#include "../p/riscv_test.h"
 
-//-----------------------------------------------------------------------
-// Begin Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_RV64U                                                    \
-
-#define RVTEST_FP_ENABLE                                                \
-  setpcr cr0, 2;                                                        \
-  mfpcr a0, cr0;                                                        \
-  and   a0, a0, 2;                                                      \
-  beqz  a0, 1f;                                                         \
-  mtfsr x0;                                                             \
-1:
-
-#define RVTEST_VEC_ENABLE                                               \
-  mfpcr a0, cr0;                                                        \
-  ori   a0, a0, 4;                                                      \
-  mtpcr a0, cr0;                                                        \
-  li    a0, 0xff;                                                       \
-  mtpcr a0, cr18;                                                       \
-
-#define RVTEST_CODE_BEGIN                                               \
-        .text;                                                          \
-        .align  4;                                                      \
-        .global _start;                                                 \
-_start:                                                                 \
-        RVTEST_FP_ENABLE                                                \
-        RVTEST_VEC_ENABLE                                               \
-        mfpcr a0, cr10; 1: bnez a0, 1b;                                 \
-        ENABLE_TIMER_INTERRUPT                                          \
-
-//-----------------------------------------------------------------------
-// End Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_CODE_END                                                 \
-        XCPT_HANDLER                                                    \
-
-//-----------------------------------------------------------------------
-// Pass/Fail Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_PASS                                                     \
-        fence;                                                          \
-        li  x1, 1;                                                      \
-        mtpcr x1, cr30;                                                 \
-1:      b 1b;                                                           \
-
-#define RVTEST_FAIL                                                     \
-        fence;                                                          \
-        beqz x28, 1f;                                                   \
-        sll x28, x28, 1;                                                \
-        or x28, x28, 1;                                                 \
-        mtpcr x28, cr30;                                                \
-1:      b 1b;                                                           \
+#undef EXTRA_INIT
+#define EXTRA_INIT                                                      \
+  ENABLE_TIMER_INTERRUPT;                                               \
+  b 6f;                                                                 \
+  XCPT_HANDLER;                                                         \
+6:
 
 //-----------------------------------------------------------------------
 // Data Section Macro
 //-----------------------------------------------------------------------
 
-#define RVTEST_DATA_BEGIN                                               \
-        .align 3; \
+#undef EXTRA_DATA
+#define EXTRA_DATA                 \
+        .align 3;                  \
 regspill:                          \
         .dword 0xdeadbeefcafebabe; \
         .dword 0xdeadbeefcafebabe; \
@@ -124,11 +76,6 @@ evac:                              \
         .dword 0xdeadbeefcafebabe; \
         .dword 0xdeadbeefcafebabe; \
 
-#define RVTEST_DATA_END
-
-//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
-//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
-
 //-----------------------------------------------------------------------
 // Misc
 //-----------------------------------------------------------------------
@@ -139,14 +86,14 @@ evac:                              \
         li a1, SR_ET|SR_IM;          \
         or a0,a0,a1;                 \
         mtpcr a0,ASM_CR(PCR_SR);     \
-        la a0,handler;               \
+        la a0,_handler;              \
         mtpcr a0,ASM_CR(PCR_EVEC);   \
         mtpcr x0,ASM_CR(PCR_COUNT);  \
         addi a0,x0,60;               \
         mtpcr a0,ASM_CR(PCR_COMPARE);\
 
 #define XCPT_HANDLER \
-handler: \
+_handler: \
         mtpcr a0,ASM_CR(PCR_K0);     \
         mtpcr a1,ASM_CR(PCR_K1);     \
         la a0,regspill;              \
@@ -171,48 +118,48 @@ handler: \
         vsetvl a1,a1;                \
         vxcpthold;                   \
         li a5,0;                     \
-handler_loop: \
+_handler_loop: \
         ld a1,0(a0);                 \
         addi a0,a0,8;                \
-        blt a1,x0,done;              \
+        blt a1,x0,_done;             \
         srli a2,a1,32;               \
         andi a2,a2,0x1;              \
-        beq a2,x0,vcnt;              \
-vcmd: \
-        beq a5,x0,vcmd_skip;         \
+        beq a2,x0,_vcnt;             \
+_vcmd: \
+        beq a5,x0,_vcmd_skip;        \
         venqcmd a4,a3;               \
-vcmd_skip: \
+_vcmd_skip: \
         li a5,1;                     \
         move a4,a1;                  \
         srli a3,a4,36;               \
         andi a3,a3,0x1;              \
-vimm1: \
+_vimm1: \
         srli a2,a4,35;               \
         andi a2,a2,0x1;              \
-        beq a2,x0,vimm2;             \
+        beq a2,x0,_vimm2;            \
         ld a1,0(a0);                 \
         addi a0,a0,8;                \
         venqimm1 a1,a3;              \
-vimm2: \
+_vimm2: \
         srli a2,a4,34;               \
         andi a2,a2,0x1;              \
-        beq a2,x0,end;               \
+        beq a2,x0,_end;              \
         ld a1,0(a0);                 \
         addi a0,a0,8;                \
         venqimm2 a1,a3;              \
-        j end;                       \
-vcnt: \
+        j _end;                      \
+_vcnt: \
         ld a2,0(a0);                 \
         srli a2,a2,31;               \
         andi a2,a2,0x2;              \
         or a3,a3,a2;                 \
         venqcnt a1,a3;               \
-end: \
-        j handler_loop;              \
-done: \
-        beq a5,x0,done_skip;         \
+_end: \
+        j _handler_loop;             \
+_done: \
+        beq a5,x0,_done_skip;        \
         venqcmd a4,a3;               \
-done_skip: \
+_done_skip: \
         la a0,regspill;              \
         ld a2,0(a0);                 \
         ld a3,8(a0);                 \