verific: Fix conditions of SVAs with explicit clocks within procedures

[yosys.git] / frontends / verific / verific.h

diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index 416b26396c84952ec0f8f7ec382bb409c609d121..695c04f3bcba3ae5451008ef8d7c196f91ff73fe 100644 (file)
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -44,6 +44,7 @@ struct VerificClocking {
        SigBit disable_sig = State::S0;
        bool posedge = true;
        bool gclk = false;
+       bool cond_pol = true;
 
        VerificClocking() { }
        VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false);