Add Tercel PHY reset synchronization

[microwatt.git] / icache.vhdl

diff --git a/icache.vhdl b/icache.vhdl
index 37a230d24e4072ee08c3d6c7a1bf813c880620fa..a658783c84ea32351e67a9c5c17cef91deec34a5 100644 (file)
--- a/icache.vhdl
+++ b/icache.vhdl
@@ -565,6 +565,7 @@ begin
        i_out.stop_mark <= r.hit_smark;
         i_out.fetch_failed <= r.fetch_failed;
         i_out.big_endian <= r.big_endian;
+        i_out.next_predicted <= i_in.predicted;
 
        -- Stall fetch1 if we have a miss on cache or TLB or a protection fault
        stall_out <= not (is_hit and access_ok);