Add Tercel PHY reset synchronization

[microwatt.git] / icache.vhdl

diff --git a/icache.vhdl b/icache.vhdl
index a0c061281592e8c899ea63fc34a0ec724584bd71..a658783c84ea32351e67a9c5c17cef91deec34a5 100644 (file)
--- a/icache.vhdl
+++ b/icache.vhdl
@@ -176,6 +176,7 @@ architecture rtl of icache is
        hit_nia   : std_ulogic_vector(63 downto 0);
        hit_smark : std_ulogic;
        hit_valid : std_ulogic;
+        big_endian: std_ulogic;
 
        -- Cache miss state (reload state machine)
         state            : state_t;
@@ -499,7 +500,7 @@ begin
         -- last cycle, and we don't want the first 32-bit chunk, then we can
         -- keep the data we read last cycle and just use that.
         if unsigned(i_in.nia(INSN_BITS+2-1 downto 2)) /= 0 then
-            use_previous <= i_in.sequential and r.hit_valid;
+            use_previous <= i_in.req and i_in.sequential and r.hit_valid;
         else
             use_previous <= '0';
         end if;
@@ -563,6 +564,8 @@ begin
        i_out.nia <= r.hit_nia;
        i_out.stop_mark <= r.hit_smark;
         i_out.fetch_failed <= r.fetch_failed;
+        i_out.big_endian <= r.big_endian;
+        i_out.next_predicted <= i_in.predicted;
 
        -- Stall fetch1 if we have a miss on cache or TLB or a protection fault
        stall_out <= not (is_hit and access_ok);
@@ -603,6 +606,7 @@ begin
                 -- Send stop marks and NIA down regardless of validity
                 r.hit_smark <= i_in.stop_mark;
                 r.hit_nia <= i_in.nia;
+                r.big_endian <= i_in.big_endian;
             end if;
        end if;
     end process;