Add Tercel PHY reset synchronization

[microwatt.git] / icache_tb.vhdl

diff --git a/icache_tb.vhdl b/icache_tb.vhdl
index 09a644b5c2f33fac2174d3fd14fb536ee5be5c75..1d179d68f94be8b180d383751fb6280b989539f3 100644 (file)
--- a/icache_tb.vhdl
+++ b/icache_tb.vhdl
@@ -13,7 +13,7 @@ architecture behave of icache_tb is
     signal rst          : std_ulogic;
 
     signal i_out        : Fetch1ToIcacheType;
-    signal i_in         : IcacheToFetch2Type;
+    signal i_in         : IcacheToDecode1Type;
 
     signal m_out        : MmuToIcacheType;
 
@@ -33,7 +33,9 @@ begin
             i_in => i_out,
             i_out => i_in,
             m_in => m_out,
+            stall_in => '0',
            flush_in => '0',
+            inval_in => '0',
             wishbone_out => wb_bram_in,
             wishbone_in => wb_bram_out
             );
@@ -147,8 +149,6 @@ begin
 
         i_out.req <= '0';
 
-        assert false report "end of test" severity failure;
-        wait;
-
+        std.env.finish;
     end process;
 end;