signal rst : std_ulogic;
signal i_out : Fetch1ToIcacheType;
- signal i_in : IcacheToFetch2Type;
+ signal i_in : IcacheToDecode1Type;
signal m_out : MmuToIcacheType;
i_in => i_out,
i_out => i_in,
m_in => m_out,
+ stall_in => '0',
flush_in => '0',
+ inval_in => '0',
wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out
);
i_out.req <= '0';
- assert false report "end of test" severity failure;
- wait;
-
+ std.env.finish;
end process;
end;