signal clk : std_ulogic;
signal rst : std_ulogic;
- signal i_out : Fetch2ToIcacheType;
- signal i_in : IcacheToFetch2Type;
+ signal i_out : Fetch1ToIcacheType;
+ signal i_in : IcacheToDecode1Type;
+
+ signal m_out : MmuToIcacheType;
signal wb_bram_in : wishbone_master_out;
signal wb_bram_out : wishbone_slave_out;
begin
icache0: entity work.icache
generic map(
- LINE_SIZE_DW => 8,
+ LINE_SIZE => 64,
NUM_LINES => 4
)
port map(
rst => rst,
i_in => i_out,
i_out => i_in,
+ m_in => m_out,
+ stall_in => '0',
+ flush_in => '0',
+ inval_in => '0',
wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out
);
-- BRAM Memory slave
- bram0: entity work.mw_soc_memory
+ bram0: entity work.wishbone_bram_wrapper
generic map(
- MEMORY_SIZE => 128,
+ MEMORY_SIZE => 1024,
RAM_INIT_FILE => "icache_test.bin"
)
port map(
stim: process
begin
i_out.req <= '0';
- i_out.addr <= (others => '0');
+ i_out.nia <= (others => '0');
+ i_out.stop_mark <= '0';
+
+ m_out.tlbld <= '0';
+ m_out.tlbie <= '0';
+ m_out.addr <= (others => '0');
+ m_out.pte <= (others => '0');
- wait for 4*clk_period;
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
i_out.req <= '1';
- i_out.addr <= x"0000000000000004";
+ i_out.nia <= x"0000000000000004";
wait for 30*clk_period;
+ wait until rising_edge(clk);
- assert i_in.ack = '1';
- assert i_in.insn = x"00000001";
+ assert i_in.valid = '1' severity failure;
+ assert i_in.insn = x"00000001"
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000001"
+ severity failure;
i_out.req <= '0';
- wait for clk_period;
+ wait until rising_edge(clk);
-- hit
i_out.req <= '1';
- i_out.addr <= x"0000000000000008";
- wait for clk_period/2;
- assert i_in.ack = '1';
- assert i_in.insn = x"00000002";
- wait for clk_period/2;
+ i_out.nia <= x"0000000000000008";
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ assert i_in.valid = '1' severity failure;
+ assert i_in.insn = x"00000002"
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000002"
+ severity failure;
+ wait until rising_edge(clk);
-- another miss
i_out.req <= '1';
- i_out.addr <= x"0000000000000040";
+ i_out.nia <= x"0000000000000040";
wait for 30*clk_period;
+ wait until rising_edge(clk);
- assert i_in.ack = '1';
- assert i_in.insn = x"00000010";
+ assert i_in.valid = '1' severity failure;
+ assert i_in.insn = x"00000010"
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000010"
+ severity failure;
-- test something that aliases
i_out.req <= '1';
- i_out.addr <= x"0000000000000100";
- wait for clk_period/2;
- assert i_in.ack = '0';
- wait for clk_period/2;
+ i_out.nia <= x"0000000000000100";
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ assert i_in.valid = '0' severity failure;
+ wait until rising_edge(clk);
wait for 30*clk_period;
+ wait until rising_edge(clk);
- assert i_in.ack = '1';
- assert i_in.insn = x"00000040";
+ assert i_in.valid = '1' severity failure;
+ assert i_in.insn = x"00000040"
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000040"
+ severity failure;
i_out.req <= '0';
- assert false report "end of test" severity failure;
- wait;
-
+ std.env.finish;
end process;
end;