use CSRRWI for CLR SV CSRs

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 18de70d98217ddc5fc7d0cbf3f89c3c1f0683202..07c4e3dea00a8186688219f6b92bb5da7d7d4870 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -29,6 +29,8 @@
         li     x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
         csrrw  x0, 0x4f8, x1
 
+// series of macros that set one, two or three register (or predicate)
+// key-value table entries that alter the behaviour of the registers
 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
         csrrw  x0, 0x4c0, x1
@@ -53,10 +55,16 @@
         li     x1, c1 | ((c2)<<16U); \
         csrrw  x0, 0x4c8, x1
 
-#define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+// clears the 2 CSRs set above
+#define CLR_SV_CSRS( ) csrrwi   x0, 0x4c0, 0xf;
 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
+// set maximum vector length.
 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
+
+// set actual vector length: normally that would
+// be vl = xN = min(mvl, min(vl, xN) however we
+// pass in x0 here.
 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
 
 #define SV_LD_DATA( reg, from, offs ) \
@@ -77,11 +85,11 @@
 
 #define TEST_SV_IMMW( reg, imm ) \
         li      t6, MASK_XLEN(imm) ; \
-        bne     reg, t6, fail
+        bne     reg, t6, fail;
 
 #define TEST_SV_IMM( reg, imm ) \
         li      t6, ((imm) & 0xffffffffffffffff); \
-        bne     reg, t6, fail
+        bne     reg, t6, fail;
 
 #define TEST_SV_FD( flags, freg, from, offs ) \
         fsflags x2, x0; \
@@ -90,7 +98,7 @@
         la      x1, from; \
         ld      x1, offs(x1); \
         fmv.x.d x2, freg; \
-        bne     x2, x1, fail
+        bne     x2, x1, fail;
 
 #define TEST_SV_FW( flags, freg, from, offs ) \
         fsflags x2, x0; \
@@ -99,7 +107,7 @@
         la      x1, from; \
         lw      x1, offs(x1); \
         fmv.x.s x2, freg; \
-        bne     x2, x1, fail
+        bne     x2, x1, fail;
 
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1