add rv64ud sv fadd test, shows flaw in loop for 3-arg operands

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index d77287403e2c96b1a2b4c2c14773bed78751a4d4..23feaa1c287a3372aa7ad1ba049b3289dda37797 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -8,7 +8,16 @@
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
+        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
+        csrrw  x0, 0x4c8, x1
+
+#define SET_SV_2CSRS( c1, c2 ) \
+        li     x1, c1 | ((c2)<<16); \
+        csrrw  x0, 0x4c0, x1
+
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+#define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val
@@ -17,6 +26,19 @@
         la      x1, from; \
         lw      reg, offs(x1)
 
+#define SV_FLD_DATA( reg, from, offs ) \
+        la      x1, from; \
+        fld     reg, offs(x1)
+
 #define TEST_SV_IMM( reg, imm ) \
         li      x1, imm; \
         bne     reg, x1, fail
+
+#define TEST_SV_FD( flags, freg, from, offs ) \
+        fsflags x2, x0; \
+        li      x1, flags; \
+        bne     x2, x1, fail; \
+        la      x1, from; \
+        ld      x1, offs(x1); \
+        fmv.x.d x2, freg; \
+        bne     x2, x1, fail