Updating SV_ELWIDTH_TEST to account for element with when loading test elements

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 543f0c3b9c99935a1d54aa38be63b9a4dd043f84..5459c354eeb62625d86b64458e9e4a3151b77e69 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -56,7 +56,7 @@
         csrrw  x0, 0x4c8, x1
 
 // clears the 2 CSRs set above
-#define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+#define CLR_SV_CSRS( ) csrrwi   x0, 0x4c0, 0xf;
 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
 // set maximum vector length.
@@ -109,6 +109,36 @@
         fmv.x.s x2, freg; \
         bne     x2, x1, fail;
 
+#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+                         expect1, expect2, expect3 )                   \
+                                                                       \
+        load_instruction( x12, testdata   , 0);                             \
+        load_instruction( x13, testdata+elwidth , 0);                             \
+        load_instruction( x14, testdata+elwidth*2, 0);                             \
+        load_instruction( x15, testdata+elwidth*3, 0);                             \
+        load_instruction( x16, testdata+elwidth*4, 0);                             \
+        load_instruction( x17, testdata++elwidth*5, 0);                             \
+                                                                               \
+        li x28, 0xa5a5a5a5a5a5a5a5;                                     \
+        li x29, 0xa5a5a5a5a5a5a5a5;                                     \
+        li x30, 0xa5a5a5a5a5a5a5a5;                                     \
+                                                                               \
+        SET_SV_MVL( vl );                                              \
+        SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),            \
+                      SV_REG_CSR( 1, 12, wid2, 12, isvec2),            \
+                      SV_REG_CSR( 1, 28, wid3, 28, isvec3));           \
+        SET_SV_VL( vl );                                               \
+                                                                       \
+        code   x28, x15, x12;                                          \
+                                                                       \
+        CLR_SV_CSRS();                                                         \
+        SET_SV_VL( 1);                                                 \
+        SET_SV_MVL( 1);                                                \
+                                                                       \
+        TEST_SV_IMM( x28, expect1 );                                   \
+        TEST_SV_IMM( x29, expect2 );                                   \
+        TEST_SV_IMM( x30, expect3 );                                   \
+
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1
 #define SV_W_16BIT 2