add fp add elwidth single-precision test

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index d77287403e2c96b1a2b4c2c14773bed78751a4d4..6c671df0e17cf5851238ee442480cba5ba435ba1 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,22 +1,73 @@
-#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
-  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
+#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
+  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
+#define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
+  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
 
-#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
-  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
+#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
+        csrrw  x0, 0x4c0, x1
+
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
+        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
+        csrrw  x0, 0x4c8, x1
+
+#define SET_SV_2CSRS( c1, c2 ) \
+        li     x1, c1 | ((c2)<<16U); \
+        csrrw  x0, 0x4c0, x1
 
-#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
-        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
+#define SET_SV_3CSRS( c1, c2 , c3 ) \
+        li     x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_2PREDCSRS( c1, c2 ) \
+        li     x1, c1 | ((c2)<<16U); \
+        csrrw  x0, 0x4c8, x1
+
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+#define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
-#define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
-#define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val
+#define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
+#define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
 
 #define SV_LD_DATA( reg, from, offs ) \
         la      x1, from; \
         lw      reg, offs(x1)
 
+#define SV_LDD_DATA( reg, from, offs ) \
+        la      x1, from; \
+        ld      reg, offs(x1)
+
+#define SV_FLD_DATA( reg, from, offs ) \
+        la      x1, from; \
+        fld     reg, offs(x1)
+
+#define SV_FLW_DATA( reg, from, offs ) \
+        la      x1, from; \
+        flw     reg, offs(x1)
+
 #define TEST_SV_IMM( reg, imm ) \
-        li      x1, imm; \
-        bne     reg, x1, fail
+        li      t6, ((imm) & 0xffffffffffffffff); \
+        bne     reg, t6, fail
+
+#define TEST_SV_FD( flags, freg, from, offs ) \
+        fsflags x2, x0; \
+        li      x1, flags; \
+        bne     x2, x1, fail; \
+        la      x1, from; \
+        ld      x1, offs(x1); \
+        fmv.x.d x2, freg; \
+        bne     x2, x1, fail
+
+#define TEST_SV_FW( flags, freg, from, offs ) \
+        fsflags x2, x0; \
+        li      x1, flags; \
+        bne     x2, x1, fail; \
+        la      x1, from; \
+        lw      x1, offs(x1); \
+        fmv.x.s x2, freg; \
+        bne     x2, x1, fail
+
+#define SV_W_DFLT 0
+#define SV_W_8BIT 1
+#define SV_W_16BIT 2
+#define SV_W_32BIT 3