fmv.x.s x2, freg; \
bne x2, x1, fail;
+#define SV_ELWIDTH_NONLOAD_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3 ) \
+ SV_ELDWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code x28, x15, x12) \
+
+#define SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code... ) \
+ \
+ load_instruction( x12, testdata , 0); \
+ load_instruction( x13, testdata+elwidth , 0); \
+ load_instruction( x14, testdata+elwidth*2, 0); \
+ load_instruction( x15, testdata+elwidth*3, 0); \
+ load_instruction( x16, testdata+elwidth*4, 0); \
+ load_instruction( x17, testdata++elwidth*5, 0); \
+ \
+ li x28, 0xa5a5a5a5a5a5a5a5; \
+ li x29, 0xa5a5a5a5a5a5a5a5; \
+ li x30, 0xa5a5a5a5a5a5a5a5; \
+ \
+ SET_SV_MVL( vl ); \
+ SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \
+ SV_REG_CSR( 1, 12, wid2, 12, isvec2), \
+ SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \
+ SET_SV_VL( vl ); \
+ \
+ code; \
+ \
+ CLR_SV_CSRS(); \
+ SET_SV_VL( 1); \
+ SET_SV_MVL( 1); \
+ \
+ TEST_SV_IMM( x28, expect1 ); \
+ TEST_SV_IMM( x29, expect2 ); \
+ TEST_SV_IMM( x30, expect3 ); \
+
#define SV_W_DFLT 0
#define SV_W_8BIT 1
#define SV_W_16BIT 2