fmv.x.s x2, freg; \
bne x2, x1, fail;
-#define SV_ELWIDTH_TEST(code, testdata, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
- expect1, expect2, expect3 ) \
+#define SV_ELWIDTH_NONLOAD_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3 ) \
+ SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code x28, x15, x12) \
+
+#define SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code... ) \
\
- SV_LDD_DATA( x12, testdata , 0); \
- SV_LDD_DATA( x13, testdata+8 , 0); \
- SV_LDD_DATA( x14, testdata+16, 0); \
- SV_LDD_DATA( x15, testdata+24, 0); \
- SV_LDD_DATA( x16, testdata+32, 0); \
- SV_LDD_DATA( x17, testdata+40, 0); \
+ load_instruction( x12, testdata , 0); \
+ load_instruction( x13, testdata+elwidth , 0); \
+ load_instruction( x14, testdata+elwidth*2, 0); \
+ load_instruction( x15, testdata+elwidth*3, 0); \
+ load_instruction( x16, testdata+elwidth*4, 0); \
+ load_instruction( x17, testdata++elwidth*5, 0); \
\
li x28, 0xa5a5a5a5a5a5a5a5; \
li x29, 0xa5a5a5a5a5a5a5a5; \
SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \
SET_SV_VL( vl ); \
\
- code x28, x15, x12; \
+ code; \
\
CLR_SV_CSRS(); \
SET_SV_VL( 1); \