Update to new privileged spec

[riscv-tests.git] / isa / rv32si / ma_fetch.S

diff --git a/isa/rv32si/ma_fetch.S b/isa/rv32si/ma_fetch.S
index f31063010bc2cac49c1de69aa4f9df568ca71520..4aa7973fd805fc3852a0792ee6267155780315d2 100644 (file)
--- a/isa/rv32si/ma_fetch.S
+++ b/isa/rv32si/ma_fetch.S
@@ -13,8 +13,8 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   li TESTNUM, 2
   la t0, 1f
@@ -38,17 +38,17 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec:
+stvec:
   li t0, 3
   beq TESTNUM, t0, fail
 
   li t1, CAUSE_MISALIGNED_FETCH
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
   li t1, 0
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 2 // skip over instruction after jalr
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END