Simplify fence.i test for RVC

[riscv-tests.git] / isa / rv64mi / dirty.S

diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 522812977a8fe5496f3e2bd7213fd45c59d8d163..0314cf5acbfc64914e89b388e90fc856f088ae0b 100644 (file)
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -44,7 +44,7 @@ RVTEST_CODE_BEGIN
 
   # Make sure R and D bits are set
   lw t0, page_table_2
-  li t1, PTE_R | PTE_D
+  li t1, PTE_A | PTE_D
   and t0, t0, t1
   bne t0, t1, die
   
@@ -52,13 +52,14 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   csrr t0, scause
   li t1, 2
   bne TESTNUM, t1, 1f
   # Make sure R bit is set
   lw t0, page_table_1
-  li t1, PTE_R
+  li t1, PTE_A
   and t0, t0, t1
   bne t0, t1, die
 
@@ -76,11 +77,17 @@ stvec_handler:
 die:
   RVTEST_FAIL
 
-.data
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
 .align 12
-page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URX_SRX
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
 dummy: .dword 0
 .align 12
-page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URWX_SRWX
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
 
-RVTEST_CODE_END
+RVTEST_DATA_END