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ERET -> xRET; new memory map
[riscv-tests.git] / isa / rv64si / ma_fetch.S
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index db702d96773c8ba7cc03eddc291cb46dbec99770..a97eecb6cbf394d2604250a87fbc737dca40e666 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
 #endif