Make sure that code is 4-byte aligned before disabling rvc (#100)

[riscv-tests.git] / isa / rv64si / ma_fetch.S

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index 594345687a83fc1436ae7cfc3e02bdfe7780fbb0..cd5a22d72077a768ff6e9753ec56c7e84fbc2990 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -23,6 +23,7 @@ RVTEST_CODE_BEGIN
   #define stvec_handler mtvec_handler
 #endif
 
+  .align 2
   .option norvc
 
   # Without RVC, the jalr should trap, and the handler will skip ahead.