ERET -> xRET; new memory map

[riscv-tests.git] / isa / rv64si / scall.S

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 703de0b5a8895efbb60dcc5efb599233453e3b1f..f4752d15e9dd05027e407bd612baa3d403eed58b 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
   #undef SSTATUS_SPP
   #define SSTATUS_SPP MSTATUS_MPP
@@ -29,9 +30,10 @@ RVTEST_CODE_BEGIN
   csrc sstatus, t0
   la t0, 1f
   csrw sepc, t0
-  eret
+  sret
 1:
 
+  li TESTNUM, 1
   scall
   j fail