revamp hwacha tests

[riscv-tests.git] / isa / rv64sv / illegal_tvec_cmd.S

diff --git a/isa/rv64sv/illegal_tvec_cmd.S b/isa/rv64sv/illegal_tvec_cmd.S
index d6d8d38cfb2986efc7061c03ddd4780b2a52626c..8943d860107a1f59a344dc191316f5ab01c845d1 100644 (file)
--- a/isa/rv64sv/illegal_tvec_cmd.S
+++ b/isa/rv64sv/illegal_tvec_cmd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
@@ -30,7 +31,7 @@ RVTEST_CODE_BEGIN
   venqcmd a3, x0
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   lw x2, 0(x1)
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5