Add another FP recoding test case

[riscv-tests.git] / isa / rv64sv / illegal_tvec_regid.S

diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index 70a6c27a6e3d92927b2f3f597535000333b4b65d..30403baaf88c175ede1c209221e3eb4ea7885caa 100644 (file)
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # illegal_tvec_regid.S
 #-----------------------------------------------------------------------------
@@ -8,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA
-  csrs status, a0
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
   TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
 
@@ -28,6 +21,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data