revamp hwacha tests

[riscv-tests.git] / isa / rv64sv / illegal_vt_inst.S

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index d749104cda88dd5977589bc8b3cedd8d32e57add..d0e5574ee19067306add40296b99e117602688cd 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -29,7 +30,7 @@ RVTEST_CODE_BEGIN
   vld vx3,a4
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5