Add another FP recoding test case

[riscv-tests.git] / isa / rv64sv / ma_utld.S

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 7b5db04ea61dd21bd677a280c0f1218e430e4d27..5ea6ee6d52a92ced7b34d05fde2d4763cdc4b732 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # ma_utld.S
 #-----------------------------------------------------------------------------
@@ -8,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  mfpcr a3,cr0
-  li a4,1
-  slli a5,a4,8
-  or a3,a3,a4 # enable traps
-  mtpcr a3,cr0
-
-  la a3,handler
-  mtpcr a3,cr3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -38,18 +31,18 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
-  mfpcr a3,cr6
-  li a4,28
+  csrr a3, scause
+  li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  mfpcr a3,cr2
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
@@ -70,16 +63,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL