+# See LICENSE for license details.
+
#*****************************************************************************
# ma_utld.S
#-----------------------------------------------------------------------------
#include "riscv_test.h"
#include "test_macros.h"
-RVTEST_RV64S
+RVTEST_RV64SV
RVTEST_CODE_BEGIN
- mfpcr a3,cr0
- li a4,1
- slli a5,a4,8
- or a3,a3,a4 # enable traps
- mtpcr a3,cr0
-
- la a3,handler
- mtpcr a3,cr3 # set exception handler
-
+ vsetcfg 32,0
li a3,4
- vvcfgivl a3,a3,32,0
+ vsetvl a3,a3
la a3, dest+1
vmsv vx1, a3
lui a0,%hi(vtcode1)
vf %lo(vtcode1)(a0)
- fence.v.l
+ fence
vtcode1:
lw x2, 0(x1)
add x2,x2,x3
stop
-handler:
+stvec_handler:
vxcptkill
- li x28,2
+ li TESTNUM,2
# check cause
- mfpcr a3,cr6
- li a4,28
+ csrr a3, scause
+ li a4,HWACHA_CAUSE_MISALIGNED_LOAD
bne a3,a4,fail
# check vec irq aux
- mfpcr a3,cr2
+ csrr a3, sbadaddr
la a4,dest+1
bne a3,a4,fail
# make sure vector unit has cleared out
+ vsetcfg 32,0
li a3,4
- vvcfgivl a3,a3,32,0
+ vsetvl a3,a3
la a3,src1
la a4,src2
vf %lo(vtcode2)(a0)
la a5,dest
vsd vx2,a5
- fence.v.l
+ fence
ld a1,0(a5)
li a2,5
- li x28,2
+ li TESTNUM,2
bne a1,a2,fail
ld a1,8(a5)
- li x28,3
+ li TESTNUM,3
bne a1,a2,fail
ld a1,16(a5)
- li x28,4
+ li TESTNUM,4
bne a1,a2,fail
ld a1,24(a5)
- li x28,5
+ li TESTNUM,5
bne a1,a2,fail
TEST_PASSFAIL