Add another FP recoding test case

[riscv-tests.git] / isa / rv64sv / privileged_inst.S

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index ef50188b3f72bf95880b1e88845822977da6a19f..e59d361fd4562410d2288f7d05248d8a915e9984 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # illegal_tvec_cmd.S
 #-----------------------------------------------------------------------------
@@ -8,24 +10,15 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
-  la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
-  la a0, SR_U64
-  csrs status, a0
-  csrc status, SR_S
+  li a3, SSTATUS_PS
+  csrc sstatus, a3
+  la t0, 1f
+  csrw sepc, t0
+  sret
+1:
 
 privileged_inst:
   vxcptcause a3 # privileged inst
@@ -34,18 +27,18 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4, privileged_inst
   lw a5, 0(a4)
   bne a3,a5,fail