RVTEST_RV64UF # Define TVM used by program.
+#define SV_ELWIDTH_TESTW( inst, vl, elwidth, wid1, wid2, \
+ testdata, ans ) \
+ \
+ la x12, testdata ; \
+ la x13, (testdata+elwidth); \
+ la x14, (testdata+elwidth*2); \
+ la x15, (testdata+elwidth*3); \
+ la x16, (testdata+elwidth*4); \
+ la x17, (testdata+elwidth*5); \
+ \
+ li x1, 0xa5a5a5a5a5a5a5a5; \
+ fmv.d.x f25, x1; \
+ fmv.d.x f26, x1; \
+ fmv.d.x f27, x1; \
+ fmv.d.x f28, x1; \
+ fmv.d.x f29, x1; \
+ fmv.d.x f30, x1; \
+ \
+ SET_SV_MVL( vl); \
+ SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1), \
+ SV_REG_CSR( 0, 25, wid2, 25, 1)); \
+ SET_SV_VL( vl ); \
+ \
+ inst f25, 0(x12); \
+ \
+ CLR_SV_CSRS(); \
+ SET_SV_VL( 1); \
+ SET_SV_MVL( 1); \
+ \
+ TEST_SV_FW(0, f25, ans, 0); \
+ TEST_SV_FW(0, f26, ans, 4); \
+ TEST_SV_FW(0, f27, ans, 8);
+
#define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \
testdata, ans ) \
\
SET_SV_VL( 1); \
SET_SV_MVL( 1); \
\
- TEST_SV_FW(0, f28, ans, 0); \
- TEST_SV_FW(0, f29, ans, 8); \
- TEST_SV_FW(0, f30, ans, 16);
+ TEST_SV_FD(0, f28, ans, 0); \
+ TEST_SV_FD(0, f29, ans, 8); \
+ TEST_SV_FD(0, f30, ans, 16);
# SV test: vector-vector add
#
RVTEST_CODE_BEGIN # Start of test code.
SV_ELWIDTH_TEST( fld , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
-/*
- SV_ELWIDTH_TEST( ld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1,
- 0x8979695949392919, 0x8777675747372717, 0x8676665646362616 )
- SV_ELWIDTH_TEST( ld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata1,
- 0x0000000000002919, 0x0000000000004939, 0x0000000000006959 )
- SV_ELWIDTH_TEST( ld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata1,
- 0x0000493900002919, 0xffff897900006959, 0xa5a5a5a500002717 )
- SV_ELWIDTH_TEST( ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1,
- 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5 )
- SV_ELWIDTH_TEST( ld , 7, 8, SV_W_16BIT, SV_W_8BIT, testdata1,
- 0xa557371779593919, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 )
- SV_ELWIDTH_TEST( ld , 11, 8, SV_W_8BIT, SV_W_16BIT, testdata1,
- 0x0049003900290019, 0xff89007900690059, 0xa5a5003700270017 )
-*/
+ SV_ELWIDTH_TEST( fld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer2 )
+ SV_ELWIDTH_TEST( fld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3)
+ SV_ELWIDTH_TEST( fld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
+ SV_ELWIDTH_TEST( fld , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
+
+
+ SV_ELWIDTH_TESTW(flw , 3, 4, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
+ SV_ELWIDTH_TESTW(flw , 3, 4, SV_W_16BIT, SV_W_DFLT, testdata3, answer8)
+ SV_ELWIDTH_TESTW(flw , 4, 4, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
+ SV_ELWIDTH_TESTW(flw , 6, 4, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
+
+ SV_ELWIDTH_TESTW(flw , 6, 4, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
+ SV_ELWIDTH_TESTW(flw , 6, 4, SV_W_DFLT, SV_W_16BIT, testdata6, answer5)
+
RVTEST_PASS # Signal success.
fail:
RVTEST_FAIL
.dword 0x8171615141312111
.dword 0x8373635343332313
+ .align 3
answer1:
.dword 0x8979695949392919
.dword 0x8777675747372717
.dword 0xa5a5a5a5a5a5a5a5
+ .align 3
+answer2:
+
+ .dword 0x8979695949392919
+ .dword 0x8777675747372717
+ .dword 0x8676665646362616
+
+ .align 3
+testdata3:
+ .dword 0x63d03c0051805140
+ .dword 0x000000000000E480
+ .dword 0x8676665646362616
+ .dword 0x8272625242322212
+ .dword 0x8171615141312111
+ .dword 0x8373635343332313
+
+ .align 3
+answer3:
+
+ .double 42.0
+ .double 44.0
+ .double 1.0
+
+ .align 3
+answer4:
+
+ .float 42.0
+ .float 44.0
+ .float 1.0
+ .float 1000.0
+ .float -1152.0
+ .word 0xa5a5a5a5
+
+ .align 3
+testdata4:
+
+ .float 42.0
+ .float 44.0
+ .float 1.0
+ .float 1000.0
+ .float -1152.0
+ .float -82.0
+ .float 0x0
+ .word 0xa5a5a5a5
+
+ .align 3
+answer5:
+
+ .short 0x5140 # 42 fp16
+ .short 0x5180 # 44 fp16
+ .short 0x3c00 # 1.0 fp16
+ .short 0x63d0 # 1000.0 fp16
+ .short 0xe480 # -1152.0 fp16
+ .short 0xd520 # -82 fp16
+ .short 0xa5a5
+ .short 0xa5a5
+ .dword 0xa5a5a5a5a5a5a5a5
+
+ .align 3
+testdata6:
+
+ .float 42.0
+ .float 44.0
+ .float 1.0
+ .float 1000.0
+ .float -1152.0
+ .float -82.0
+ .dword 0x0
+ .dword 0x0
+ .dword 0x0
+ .dword 0x0
+ .dword 0x0
+ .dword 0x0
+ .dword 0x0
+
+answer7:
+ .dword 0xa5a5a5a549392919
+ .dword 0xa5a5a5a589796959
+ .dword 0x8777675747372717
+ .dword 0xa5a5a5a5a5a5a5a5
+
+ .align 3
+
+answer8:
+
+ .float 42.0
+ .float 44.0
+ .float 1.0
+
+ .align 3
# Output data section.
RVTEST_DATA_BEGIN # Start of test output data region.
.align 3
projects / riscv-tests.git / blobdiff