augment sv_addi test using macros

[riscv-tests.git] / isa / rv64ui / sv_addi.S

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index b6493bcf3e64a9346e965932046a5fd1dc9f3ade..a78bcdc7c7f837fbb441a41640b58a8e26904511 100644 (file)
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -7,22 +7,27 @@ RVTEST_RV64U        # Define TVM used by program.
 
 # Test code region.
 RVTEST_CODE_BEGIN   # Start of test code.
-        csrrw   x0, 0x4f2, 2
-        la      x1, testdata
-        lw      x2, 0(x1)
-        la      x1, (testdata+8)
-        lw      x3, 0(x1)
-        li      x1, SV_REG_CSR(1, 2, 0, 2, 1, 0)
-        csrrw   x0, 0x4c0, x1
-        csrrw   x0, 0x4f0, 2
-        addi    x2, x2, 1         # Should be 42 into $2.
-        csrrwi  x0, 0x4f2, 0
-        csrrwi  x0, 0x4c0, 0
-        csrrwi  x0, 0x4f0, 0
-        li      x1, 42        # Desired result 1
-        bne     x2, x1, fail  # Fail out if doesn't match.
-        li      x1, 43        # Desired result 2
-        bne     x3, x1, fail  # Fail out if doesn't match.
+
+        SV_LD_DATA( x2, testdata   , 0)
+        SV_LD_DATA( x3, testdata+8 , 0)
+        SV_LD_DATA( x4, testdata+16, 0)
+        SV_LD_DATA( x5, testdata+24, 0)
+
+        SET_SV_MVL(2)
+        SET_SV_CSR(1, 3, 0, 3, 1, 0)
+        SET_SV_VL(2)
+
+        addi    x3, x3, 1
+
+        CLR_SV_CSRS()
+        SET_SV_VL(0)
+        SET_SV_MVL(0)
+
+        TEST_SV_IMM(x2, 1001) # should not be modified
+        TEST_SV_IMM(x3, 42)
+        TEST_SV_IMM(x4, 43)
+        TEST_SV_IMM(x5, 1002) # should not be modified
+
         RVTEST_PASS           # Signal success.
 fail:
         RVTEST_FAIL
@@ -33,9 +38,10 @@ RVTEST_CODE_END     # End of test code.
 .data
         .align 3
 testdata:
+        .dword 1001
         .dword 41
         .dword 42
-        .dword 43
+        .dword 1002
 
 # Output data section.
 RVTEST_DATA_BEGIN   # Start of test output data region.