add extra unit tests
[riscv-tests.git] / isa / rv64ui / sv_addw_elwidth.S
index 8da831c544e75e89d8acf0c7077c02ba552a92dd..2a6c40834186681c2b7b7d758ea361103e28ab8f 100644 (file)
@@ -8,7 +8,8 @@ RVTEST_RV64U        # Define TVM used by program.
 // TODO: move SV_ELWIDTH_TEST to sv_test_macros.h
 // TODO: probably remove testing of x15 and x16 (or pass in as extra args?)
 
-#define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2, expect3 ) \
+#define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+                         expect1, expect2, expect3 ) \
                                                         \
         SV_LDD_DATA( x12, testdata   , 0);               \
         SV_LDD_DATA( x13, testdata+8 , 0);               \
@@ -21,11 +22,11 @@ RVTEST_RV64U        # Define TVM used by program.
         li x29, 0xa5a5a5a5a5a5a5a5;                                      \
         li x30, 0xa5a5a5a5a5a5a5a5;                                      \
                                                         \
-        SET_SV_MVL( 3);                                  \
-        SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, 1),       \
-                      SV_REG_CSR( 1, 12, wid2, 12, 1),        \
-                      SV_REG_CSR( 1, 28, wid3, 28, 1));       \
-        SET_SV_VL( 3);                                   \
+        SET_SV_MVL( vl );                                  \
+        SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),       \
+                      SV_REG_CSR( 1, 12, wid2, 12, isvec2),        \
+                      SV_REG_CSR( 1, 28, wid3, 28, isvec3));       \
+        SET_SV_VL( vl );                                   \
                                                         \
         addw   x28, x15, x12;                              \
                                                         \
@@ -49,18 +50,28 @@ RVTEST_RV64U        # Define TVM used by program.
 RVTEST_CODE_BEGIN   # Start of test code.
 
         # TODO: add "addw" argument, add testdata argument
-        SV_ELWIDTH_TEST(  0, 0, 0,
+        SV_ELWIDTH_TEST(  3, 0, 0, 0, 1, 1, 1,
                 0xffffffff8b6bab8b,  0xffffffff88684828,  0x0000000000000000 )
-        SV_ELWIDTH_TEST(  0, 0, 3,
+        SV_ELWIDTH_TEST(  3, 0, 0, 3, 1, 1, 1,
                 0x886848288b6bab8b,  0xa5a5a5a500000000,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  1, 1, 0,
+        SV_ELWIDTH_TEST(  3, 1, 1, 0, 1, 1, 1,
                 0xffffffffffffff8b,  0xffffffffffffffab,  0x000000000000006b )
-        SV_ELWIDTH_TEST(  1, 1, 3,
+        SV_ELWIDTH_TEST(  3, 1, 1, 3, 1, 1, 1,
                 0xffffffabffffff8b,  0xa5a5a5a50000006b,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  1, 1, 2,
+        SV_ELWIDTH_TEST(  3, 1, 1, 2, 1, 1, 1,
                 0xa5a5006bffabff8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
-        SV_ELWIDTH_TEST(  1, 1, 1,
+        SV_ELWIDTH_TEST(  3, 1, 1, 1, 1, 1, 1,
                 0xa5a5a5a5a56bab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 0, 0, 0, 1, 1, 0,
+                0xffffffff8b6bab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 3, 3, 3, 1, 1, 0,
+                0xffffffff8b6bab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 2, 2, 3, 1, 1, 0,
+                0xffffffffffffab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 3, 2, 3, 1, 1, 0,
+                0x000000004232ab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  3, 2, 3, 3, 1, 1, 0,
+                0x000000004939ab8b,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
 
         RVTEST_PASS           # Signal success.
 fail: