Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / amomin_d.S

diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
index 01e1feb46b5695b5e62cdd8863eb937dc7b64d5d..292188415672da49839dbda49386b7ba70f079dc 100644 (file)
--- a/isa/rv64uv/amomin_d.S
+++ b/isa/rv64uv/amomin_d.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # amomin_d.S
 #-----------------------------------------------------------------------------
@@ -8,11 +10,12 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,13 +23,13 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1
 loop:
   ld a0,0(a5)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a5,a5,8
   addi a1,a1,1