Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / fmovn.S

diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index 1d6e87ee22ec3a22044511e90547fa5bc63908b4..44423701145f577bbb7d0978dbfadab34823e287 100644 (file)
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # fmovn.S
 #-----------------------------------------------------------------------------
@@ -8,17 +10,18 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,2
   li a6,2048
-  vvcfgivl a6,a6,4,2
+  vsetvl a6,a6
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a7,dest
   vfsd vf0,a7
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1
@@ -28,7 +31,7 @@ loop:
   slli a4,a4,63
   srai a4,a4,63
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1