Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / fsw.S

diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
index eaafeff4bc4a92b3fc5d1fe0b9399f9ea5a66afd..9539a775e8eece91bd118a22c339c89350df274e 100644 (file)
--- a/isa/rv64uv/fsw.S
+++ b/isa/rv64uv/fsw.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # fsw.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1
@@ -26,7 +28,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   lw a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,4