Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / imul.S

diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index 0925e59de724db46b6c513e83dab2898bc8ebe67..ebfb77d0cb68d40b7100129ddcf972ef3dc62fd1 100644 (file)
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # imul.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0
@@ -48,14 +50,14 @@ RVTEST_CODE_BEGIN
   fence
 
   li s2,40
-  li x28,2
+  li TESTNUM,2
   bne s1,s2,fail
 
   li a1,0
   li a2,0
 loop:
   ld a0,0(a5)
-  addi x28,a2,3
+  addi TESTNUM,a2,3
   bne a0,a1,fail
   addi a5,a5,8
   addi a1,a1,20