Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / lbu.S

diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 166f40e7f8b754f04c82f161c8151d3ec6710120..fd04fdfb14842d055b52fb8a9c43367cd9106def 100644 (file)
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # lbu.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
@@ -29,7 +31,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   srl a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8