Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / lw.S

diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
index 8b1563645d931c18d418562b35339cdd866f6d76..49869849c540488e4b86b0199a66982c20fc984e 100644 (file)
--- a/isa/rv64uv/lw.S
+++ b/isa/rv64uv/lw.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # lw.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0
@@ -29,7 +31,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   sra a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8