Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / lwu.S

diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
index d8b5bf2e62b91af22d08228f067ee7c761831b37..502662a272a071b5151ace9d05ed22b8ceb82b5b 100644 (file)
--- a/isa/rv64uv/lwu.S
+++ b/isa/rv64uv/lwu.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # lwu.S
 #-----------------------------------------------------------------------------
@@ -8,11 +10,12 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:
@@ -28,7 +31,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   srl a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8