Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / movn.S

diff --git a/isa/rv64uv/movn.S b/isa/rv64uv/movn.S
index 91a5a3c7adc29c8f6938d8bf6941ef056b021d0b..97b62613f2457ef713cbdcd6b8828fe743e12e48 100644 (file)
--- a/isa/rv64uv/movn.S
+++ b/isa/rv64uv/movn.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # movn.S
 #-----------------------------------------------------------------------------
@@ -8,17 +10,18 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a6,2048
-  vvcfgivl a6,a6,4,0
+  vsetvl a6,a6
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a7,dest
   vsd vx3,a7
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1