Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / vfmvv.S

diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
index 869160bb5cdfdb8f339a90e205ee4988f8669ed8..c1acfc46741a31a41a7aec698933292eef838e65 100644 (file)
--- a/isa/rv64uv/vfmvv.S
+++ b/isa/rv64uv/vfmvv.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # vfmvv.S
 #-----------------------------------------------------------------------------
@@ -8,23 +10,24 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 2,2
   li a2,2048
-  vvcfgivl a2,a2,2,2
+  vsetvl a2,a2
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   vfmvv vf1,vf0
   la a3,dest
   vfsd vf1,a3
-  fence.v.l
+  fence
 
   li a1,1
 loop:
   ld a0,0(a3)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a3,a3,8
   addi a1,a1,1
@@ -34,7 +37,7 @@ loop:
 vtcode:
   utidx x1
   addi x1,x1,1
-  mxtf.d f0,x1
+  fmv.d.x f0,x1
   stop
 
   TEST_PASSFAIL