Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / vmvv.S

diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
index 3b316b96a222ed79d01982040d6363636efa8f2a..c3529f1f09a43f6dacb214d336920077e3f94187 100644 (file)
--- a/isa/rv64uv/vmvv.S
+++ b/isa/rv64uv/vmvv.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # vmvv.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0
@@ -25,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1