Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / vvadd_fd.S

diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index 7b2ce98ea2e32898d2221b85a7e5ae7685a214d7..6a7c4b26052c57300a797487f0ce1e670d51d13c 100644 (file)
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # vvadd_fd.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32
@@ -24,19 +26,19 @@ RVTEST_CODE_BEGIN
   la a5,dest
   vfsd vf2,a5
   fence
-  la a5,result
+  la a6,result
   ld a1,0(a5)
-  ld a2,0(a5)
-  li x28,2
+  ld a2,0(a6)
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass